1. Field of the Invention
The present invention relates to a video signal processor and more particularly to a sync signal generating apparatus for a video signal processor.
2. Background of Related Art
In the United States of America, digital broadcast has been implemented on August of 1998 along with the conventional analog broadcast and a complete replacement of the analog broadcast with the digital broadcasts has been planned for the year 2006. Although, the digital broadcast has not been implemented in Europe or in Asia, the British Empire and Sweden plan to introduce digital broadcasts in the latter half of next year and a full conversion into digital broadcasts is planned for the year 2012 in all European countries. Korea plans to commence digital broadcast testing and fully convert into digital broadcasts by 2010. Finally, Japan plans to start digital broadcasts in 2000 and complete digitalization of broadcasts by 2010.
Accordingly, a television for receiving digital broadcast signals has not been fully developed. Thus, a television receiver capable of processing both the digital broadcast signal and the conventional National Television System Committee (NTSC) signal is required until the digital broadcasts fully replaces the conventional analog signal.
An NTSC image has a fixed frame rate of 59.94 Hz and uses a clock signal of 74.175 MHz. In contrast, the digital image has variable frame rates and uses a clock signal of 74.25 MHz for frame rates of 60 Hz, 30 Hz, and 24 Hz while a clock signal of 74.175 MHz is used for frame rates of 59.94 Hz, 29.97 Hz, and 23.98 Hz. By selecting the correct clock signal corresponding to the frame rate of the input data, a television receiver can appropriately operate.
Thus, the clock signal must be properly selected in order to process both the digital television image and the NTSC image. Namely, the clock for image processing should be synchronized with 59.94 Hz when the receiver displays the NTSC images while a proper clock signal should be selected according to the frame rate of input data when the receiver displays digital television images.
Although a synchronous (sync) signal for a frame rate of the transmitted NTSC image and a sync signal of the digital image processor may both be 59.94 Hz signal, the signals may not be synchronized due differences in the frequencies of the clock used. Thus, to process a NTSC image, the image processor of the digital image receiver uses a clock of 74.175 MHz corresponding to a NTSC sync signal for the frame rate of 59.94 Hz. Accordingly, difference between the synchronous signal of a NTSC image and the sync signal of the image processor is reduced.
Nonetheless, even if a clock of 74.175 MHz is utilized, the clock signals of the NTSC input image and the clock signals of the digital image processor may never be synchronized. Moreover, if the signals were synchronized, the signals may at some point become unsynchronized.
Particularly, between the two sync signals of the NTSC and the digital image, one sync signal may be ahead or be delayed relative to the other sync signal. This occurs during the transmitting and receiving of data when the data is transmitted in a wrong format. As a result, the image processor may display an incorrectly processed image obtained, for example, from a de-interlacing of wrong data.
FIGS. 1A and 1B show a case where a field sync signal of a NTSC image for timely reading and writing the NTSC image is not synchronized with the sync signal of a digital image processor. Namely, the sync signal of the NTSC image is relatively delayed when compared with the sync signal of a digital image processor.
At time T, the digital image processor should already have received the NTSC image data corresponding to the field sync signal "b" as shown in FIG. 1A in order to perform deinterlacing with the image data of the previous field, stored in advance. However, the NTSC image processor has not written data corresponding to the sync signal "b." Moreover, because the signals are not synchronized, the data of the previous field is also not correctly stored. As a result, the digital image processor performs the de-interlacing with respect to wrong image data.
To overcome this problem, a locking circuit for synchronizing the sync signal of the NTSC image and the sync signal of the digital image processor is required.